The lowest metal layers are used for source/drain and gate strapping, and for local routing of signals within a circuit block. Higher levels of metal are then used for conveying information over longer distances between blocks, and for power supply routing. Yet another good technique is to use the highest level of metal for bond pads and for options in creating multiple versions of a chip.
As a distribution network expands in a fractal manner, the propagation times to each destination may remain uniform (Fig. 2), but the overall propagation delay and power consumption will be increased.
Thus, it is preferred to distribute the clocks as global signals in high metal, then selectively enable them as local signals in a lower level of metal. Small adjustments in phase (arrival times) can be made in order to align clocks. These techniques may be compared to delay locking.
Fig. 2 Fractal distribution permits equal arrival time
of signals, but causes greater total propagation time
and power consumption. Repeaters may be included.
In a digital logic design, phase locking should be used only if no other technique will achieve the desired result. A Delay Locked Loop (DLL) is easier to stabilize because it has only one independent variable (phase.) But it places stricter limits on the frequency range. A Phase Locked Loop (PLL) must converge on two independent variables (frequency and phase) and thus is more difficult to stabilize, but it tolerates a wider range of frequency, which may be useful for power reduction.
You must have a history of experience within your organization before attempting these techniques. That means doing test chips on proposed methods before putting them into an actual product.
Cross Talk
The vertical thickness of metal lines can be greater than their horizontal width. Today’s SEM cross sections show that there is more nearly a parallel plate capacitance to the nearest neighbors than to the ground plane. Appropriate layout techniques are required to assure that the signal is not disturbed.
Co-ordinate Among Chip Sub-Sections
A wide variety of power reduction techniques are presently in use. They include various mixes of selective reduction in supply and frequency. Combinational and Sequential circuits cannot be treated in the same manner. If each section of your chip adopts a different strategy, they could interfere with each other.
You need to ensure that your chip has a consistent power-savings strategy across all sections, and that these methods will not interfere with each other. Also the power-up-clear scheme should be planned in advance, and appropriate conventions adopted for the entire chip.
It is necessary to achieve a consistent global strategy for your clocks. For example, if a sub-circuit receives a masked clock, be sure the mask is cleanly enabled so as not to produce a runt pulse when the clock is in transition. Clocks may also be divided down to lower frequencies where appropriate.
Reduced Signal Swing
The lower power and faster propagation of a reduced signal swing is best realized in scaling the main VDD supply. However, local reduction of the excursion is still beneficial in some circumstances. Fig. 3 calls attention to the power consumed in regulation. Vreg1 is a local regulated level, V1 is a signal name, and Cload is the capacitance of a long metal line. The average current is
Neglecting the power consumed by the reference generator, the power consumption in the driver and regulator combined is simply
Indicating that for local regulated signals, the power reduction is linear with the reduced signal swing, compared with a square law reduction for the case where VDD is scaled. This issue should be considered when deciding whether to regulate Vreg1 off-chip.
The Vreg1 regulator can be removed entirely (Fig. 4) but the proportionate reduction in power consumption remains about the same. These circuits would have a mechanism (not shown) to maintain the level of V2. Let the excursion of V2 be VDD / N. Then Cwire / Cdrive will be N-1. The effective driving point capacitance Ceff is then Cwire / N. The power required to operate the circuit is thus
which is 1/N of the power required for a full swing signal. Hence, the scheme of Fig. 4 also scales the power linearly, and not square law, with the signal.
Depending on context and requirements, these signals might be implemented as true/complement pairs, or as single-ended signals with some reference level.
Receiver for Small Signal Swings
A possible receiver design (Fig. 5) accepts the reduced levels on V2 and V2b , then amplifies them with cross-coupled pairs (M2/M3, M4/M5) when the information is needed. We are treating the reduced signals as information content, or data signals, as distinguished from control signals such as the clock CLK/CLKB which are at full rail levels here.
Fig. 5 Detail of receiver circuit for small signals
This design assumes that the operating level of (V2, V2b) is not above the threshold of M4/M5. (If it were, an additional clocked N-type device could be inserted in the source path of M4/M5 to prevent unnecessary current.) M6/M7 convey the signal level into (V3, V3b) with no threshold drop, because the gates (at CLKB) are at full VDD level, while (V2, V2b) are at reduced levels.
The next stage to receive the amplified signal may have signals that are valid for the full cycle, as would be (V5, V5b) in Fig. 6.
Fig. 6 Possible latch circuit for next stage
Energy Budget in Charge Transfer
Figure 7 compares several types of charge transfer. In each case, Wprovided = Wlost + Wdelivered.
The initial conditions are given as V volts on the left side and 0 volts on the right.
Each sketch must comply with conservation of energy and conservation of charge. From Fig. 7(a) arises the familiar MOS formula of P = CV2f for power consumption, which is independent of the magnitude of R, the resistance of a driver.
In Fig. 7(a) the energy lost and the energy delivered are given as (1/2)CV2 in column 7(a) of table II. While they happen to have the same numerical value, in fact they are not the same energy. One is the energy stored on the capacitance, and the other is the energy expended in the transfer process. Their sum is the energy provided, which is CV2.
In Fig. 7(b) we could also define a term Wretained of (1/8)CV2 and note that Wretained + Wprovided = (1/2)CV2, the energy stored initially on the left capacitance. The total energy stored in the two capacitances after charge sharing is equal to the amount lost in the resistance.
Fig. 7 Energy in charge transfer
